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architectures, neuromorphic computing, hardware security, and energy-efficient computer systems. The candidate will become part of the QuNeCo project, an ambitious collaboration between universities in
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at different timescales, exploring trade-offs between different design choices, quantizing the models, and implementing the best-performing ones in custom digital hardware, on FPGA and/or in an application
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deploying the face de‑identification pipeline on resource‑constrained hardware, optimizing the underlying AI models based on latency, memory, and power constraints, and building demonstrators that showcase
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Physical Layer Security and Hardware Demonstrator Development Physical-layer security is becoming increasingly important for protecting next-generation wireless networks against eavesdropping, spoofing
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assisted ISAC framework available at the TUM ACES Lab. ▪ Conducting real world experiments to analyze performance deviations between theoretical models, software simulations, and hardware behavior. ▪ Working
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amplification hardware, which becomes increasingly difficult to scale as the number of qubits grows.
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constraints into the theoretical analysis. Provide design guidelines for future experimental implementations of quantum repeater networks, specifying hardware requirements and performance benchmarks. Contribute
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. The candidate will join the System Software Group , and study the performance and scalability characteristics of adapting scientific simulation software to current and future supercomputer hardware. The research
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. Programming, coding, and experimental hardware skills (desirable). Strong analytical and mathematical capabilities. A passion for research and a willingness to learn. Excellent presentation, communication, and
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, modelling, prototyping and experimental validation. The best fit is A candidate interested in high-frequency measurement techniques, sensor hardware development and precision experimentation. PhD 2