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Hours of work: Full-time Tenure: Fixed term for 1 year We are seeking to appoint two outstanding researchers to join an ambitious, multidisciplinary research programme focused on the discovery
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research training. It is a condition that the person who accepts the position applies for and is granted admission to the faculty’s doctoral programme in PhD in Technology within three months of starting in
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NeuroPathways, and participate in interdisciplinary seminars and training activities. The PhD fellow will take part in the approved PhD program at the Faculty of Educational Sciences and is expected to complete
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Research Fellow, you must participate in an approved educational programme for a PhD degree within a period of 3 years. The deadline for applying for admission to the PhD programme at The Faculty of Science
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- 21:59 (UTC) Country Germany Type of Contract To be defined Job Status Other Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff
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The National University of Singapore invites applications for the position of Research Assistant in the Department of Computer Science, School of Computing (SoC). SoC is strongly committed
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5 Sep 2026 Job Information Organisation/Company University College Dublin Research Field Computer science » Other Computer science » Other Researcher Profile Recognised Researcher (R2) Application
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(two-year) postdoctoral fellowships (10 positions) for highly qualified candidates who have completed or will soon complete their PhD or equivalent in chemistry, data and computer science, earth sciences
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University of North Carolina at Chapel Hill | Chapel Hill, North Carolina | United States | 21 days ago
Postdoctoral Trainee - Carolina Cancer Nanotechnology Training Program Vacancy ID PDS004947 Full-time/Part-time Full-Time Temporary Hours per week 40 FTE 1 Work Location Chapel Hill, NC Position Location North
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Infrastructure? No Offer Description Mission: Conduct research in the field of quantum computing and its modular and distributed architectures based on cryogenic interconnections and leading-edge error correction