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at different timescales, exploring trade-offs between different design choices, quantizing the models, and implementing the best-performing ones in custom digital hardware, on FPGA and/or in an application
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deploying the face de‑identification pipeline on resource‑constrained hardware, optimizing the underlying AI models based on latency, memory, and power constraints, and building demonstrators that showcase
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science » Computer architecture Computer science » Computer hardware Computer science » Computer systems Computer science » Programming Researcher Profile First Stage Researcher (R1) Application Deadline 31 Aug 2026
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