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, advanced packaging, backside power delivery networks, and chiplet-based architectures require new methodologies to model and optimize system behaviour beyond the traditional chip boundary. You will develop
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modelling, high-speed device engineering, fabrication-aware optimisation and experimental validation. The final level and scope of the role will be determined based on the successful candidate's background
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algorithms. model and optimize end-to-end physical-layer performance, hardware non-idealities, and overall power consumption. focus primarily on space and security topics (satellite communications, reliable
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through performance modeling and prototyping to provide expert guidance on design and implementation of next-gen network architectures. Engage in R&D activities within project teams to take research ideas