Sort by
Refine Your Search
-
Listed
-
Country
-
Program
-
Employer
-
Field
-
ASIC implementation. You will carry out system modelling, design novel parallel processor architectures at the RTL level (using Verilog/SystemVerilog or VHDL), and drive the hardware-software co-design
-
research on open-source processor architectures and hardware accelerators, including RISC-V based designs. Design, implement, and evaluate digital ICs using Verilog/SystemVerilog and related hardware
-
station, DC and pulsed I-V, retention and endurance testing, instrument automation) Experience writing Verilog-A and/or RTL in (System)Verilog or VHDL Relevant master’s thesis or major projects aligned with
-
computer architectures and digital system design with HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. LanguagesENGLISHLevelExcellent LanguagesSPANISHLevelExcellent Research
-
, or comparable industry-standard EDA tools. You have experience with system-level modelling using MATLAB/Simulink, Verilog-A or comparable tools. You enjoy collaborating across disciplines and translating sensor
-
, Microelectronics, Computer Engineering, or a closely related field, completed by the start of the position Have a solid background in digital hardware design: Verilog/SystemVerilog RTL, logic synthesis, and place
-
hardware design: Verilog/SystemVerilog RTL, logic synthesis, and place-and-route Be familiar with Python programming Have a working proficiency in English. (Finnish language is not required.) The following
-
relevant technical software, such as Cadence, SPICE, Verilog, etc. are needed; • Background knowledge in neural network algorithms preferred, but not required • Collaborative skills, student mentorship
-
circuit design experience preferred Know how to design circuit using one or more of the software listed (Cadence; Fluent use of LT-Spice, Verilog-A, Python, ADS, ICCAP, etc.) Know how to perform circuit