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limits due to the continuous downscaling of the physical size of devices and wires to the nanometer scale. The miniaturization of circuits seems to have reached a possible halt, since transistors can only
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field effects transistors (CMOSFET) [2]. The use of atomic thick material comes with new challenges. The bond free surfaces challenge the gate dielectric deposition process with classical techniques. Also
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your goals. Your Training In addition to the PhD track at the KU Leuven, you will: Learn how to operate 300mm industrial CVD reactors. Gain knowledge from different physical characterization techniques
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on an amorphous starting surface . During this PhD research, you will embark on a journey to reveal how the geometry, chemical composition and critical (physical) dimensions of the design affect where TMD crystals