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field effects transistors (CMOSFET) [2]. The use of atomic thick material comes with new challenges. The bond free surfaces challenge the gate dielectric deposition process with classical techniques. Also
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/Nanotechnology/Computer Science/Machine Learning Good expertise in programming (python, C++) and a basic understanding of algorithms and image processing Experience with electron microscopy is a plus Knowledge in
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deposition processes of homo- and heterostructures with monolayer thickness control that can be integrated into future sub-nanometer devices such as gate-all-around nanosheet field effect transistors (FETs
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corrosion are becoming a challenging topic in many CMP processes. Wafer grinding – mainly used in 3D applications – thins down the wafer and can leave post-grinding defects that negatively impact device
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new materials and disruptive integration schemes, process innovations and structural scaling boosters (hybrid metallization, semi-damascene metallization, buried power rails enabling interconnect
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relevant industrial experience in physical design You have a solid understanding of all key building blocks of digital design and SoC architecture (from devices to logic gates, and to computer architecture
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processing for nanoelectronics applications Apply 2D layered Transition Metal Di-Chalcogenides (TMDCs) are envisioned for replacing silicon in advanced CMOS logic technology nodes, in the form of stacked
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team with various backgrounds in materials and deposition techniques, state of the art 200mm and 300mm process lines, laboratories, device learning and modelling. The PhD candidate will be part of
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nucleate and how they orient during the CVD process. You can propose various strategies to alter the chemical reactivity of starting surface by surface functionalization, and to introduce a relief or