1 hardware-design PhD positions at CNRS

M/F PhD offer on Spike Sorting algorithm implementation on Hybrid FPGA/ASIC platform for next generation of Brain Computer interfaces

CNRS | Villeneuve la Garenne, le de France | France | 3 months ago

intelligence. It promotes strong Franco-Canadian collaborations and offers an ideal framework for hardware–algorithm co-design projects. The scientific organization of the PhD project will rely on close