2 fpga PhD positions at CNRS

M/F PhD offer on Spike Sorting algorithm implementation on Hybrid FPGA/ASIC platform for next generation of Brain Computer interfaces

CNRS | Villeneuve la Garenne, le de France | France | 3 months ago

: • Digital FPGA-based architectures offering configurability and adaptability • Analog CMOS/memristor circuits providing exceptional energy efficiency and low-latency processing This hybrid approach has

M/F - PhD thesis - Advanced spectroscopy for a single-ion optical clock

CNRS | Besan on, Franche Comte | France | 2 months ago

of HR schemes, using the Artiq environment (FPGA-based experiment control) - The characterization of the clock transition coherence time, the main noise sources, and the implementation of DD sequences