1 asic PhD positions at CNRS

M/F PhD offer on Spike Sorting algorithm implementation on Hybrid FPGA/ASIC platform for next generation of Brain Computer interfaces

CNRS | Villeneuve la Garenne, le de France | France | 3 months ago

20 Jun 2026 Job Information Organisation/Company CNRS Department Institut d'Electronique de Microélectronique et de Nanotechnologie Research Field Engineering Physics Technology Researcher Profile First Stage Researcher (R1) Application Deadline 10 Jul 2026 - 23:59 (UTC) Country France Type of...