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ASIC implementation. You will carry out system modelling, design novel parallel processor architectures at the RTL level (using Verilog/SystemVerilog or VHDL), and drive the hardware-software co-design
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, or comparable industry-standard EDA tools. You have experience with system-level modelling using MATLAB/Simulink, Verilog-A or comparable tools. You enjoy collaborating across disciplines and translating sensor
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relevant technical software, such as Cadence, SPICE, Verilog, etc. are needed; • Background knowledge in neural network algorithms preferred, but not required • Collaborative skills, student mentorship
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circuit design experience preferred Know how to design circuit using one or more of the software listed (Cadence; Fluent use of LT-Spice, Verilog-A, Python, ADS, ICCAP, etc.) Know how to perform circuit