4 processor-"https:"-"https:"-"https:"-"https:"-"https:"-"https:"-"https:"-"CSIC" positions at CEA

Formal Modeling of Clock Glitch Attacks for Security Verification of Processors H/F

CEA | Tournon sur Rhone, Rhone Alpes | France | about 1 month ago

Formal Modeling of Clock Glitch Attacks for Security Verification of Processors H/F Research context Embedded processors are increasingly deployed in security-critical applications, making

Stage 4D Gaussian splatting for autonomous driving-Saclay- H/F

CEA | Corbeil Essonnes, le de France | France | about 1 hour ago

segmentation. In : 2025 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV). IEEE, 2025. p. 2250-2259. [3] KERBL, Bernhard, KOPANAS, Georgios, LEIMKÜHLER, Thomas, et al. 3d gaussian splatting

Stage Human-Object Interaction benchmarking-Saclay-H/F

CEA | Corbeil Essonnes, le de France | France | 8 days ago

on this benchmark. - Write a publication about this benchmark. #Cea List Moyens / Méthodes / Logiciels AI, Deep Neural Network, Computer Vision, Human behavior analysis Profil du candidat Profile - Students in

Co-design engineer for future computing architectures in HPC - M/F

CEA | Corbeil Essonnes, le de France | France | 3 months ago

, electronics or embedded systems. Required skills/knowledge: -HW description languages: SystemC, VHDL, Verilog, SystemVerilog, CHISEL - Knowledge of digital electronic architecture (processors, Caches, NoC