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The Technologies Cluster at the Department of Architecture seeks highly qualified applicants actively engaged in interdisciplinary research focused on, but not limited to, one or more of the
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The Role This position constitutes a very exciting and unique opportunity to mature with and help shape the design area at SUTD. Along the way, the candidate will interact with the governing bodies in Singapore, the funding agencies and the industrial eco-system. The successful candidate will...
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Position Description The successful candidate is expected to demonstrate expertise in the areas of building science and technology, with emphasis in architectural tectonics, sustainable materials
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Position Description The pillar of Architecture and Sustainable Design at the Singapore University of Technology and Design invites applications for a full-time Tenure-Track Assistant Professor
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-range ordered honeycomb architectures through phase separation technology. (2). Reveal the intrinsic mechanisms governing the electromagnetic wave absorption and thermal conduction properties through
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& Governance Engineer to join the SAGE team. In this role, you will execute safety testing, conduct red teaming exercises, review system architectures for vulnerabilities, and support governance practices. You
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computational architectures for foundation models, explore embodied AI approaches, and pioneer self-improving methodologies that push the boundaries of intelligent systems. Key Responsibilities: Lead
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, prototyping, and industry-trial priorities. Coordinate contributions from multidisciplinary and internationally distributed teams. Make or recommend technical architecture, implementation, testing, and
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architecture representing diverse personas for multilingual and multicultural population Build and evaluate persona-based simulation systems for aiding policy design Work collaboratively with the team including
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). The selected candidate is expected to work on: • physical, thermal and circuit-to-system modeling, design exploration, architecture and validation/testing framework • chip and substrate model iterative