ONE (1) research grant for candidates with master degree with reference number BI|2024/497 is now available under the scope of project UNIFY – refª 2022.06780.PTDC, funded by FUNDAÇÃO PARA CIÊNCIA E A TECNOLOGIA

14 Feb 2024
Job Information

Organisation/Company

INESC ID

Research Field

Engineering » Computer engineering
Engineering » Electrical engineering

Researcher Profile

First Stage Researcher (R1)

Country

Portugal

Application Deadline

8 Mar 2024 - 23:59 (Europe/Lisbon)

Type of Contract

Other

Job Status

Other

Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme

Reference Number

Projet UNIFY – refª 2022.06780.PTDC - BI|2024/497

Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

Public notice for research grant

Projet UNIFY – refª 2022.06780.PTDC

BI|2024/497

 

INESC-ID - Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa is a R&D institute dedicated to advanced research and development in the fields of Information Technologies, Electronics, Communications, and Energy. INESC-ID has participated in more than 50 research projects funded by the European Union and more than 190 funded by national entities. Until today, our researchers have published more than 700 papers in international journal papers, more than 3000 papers in international conferences, and have registered 15 patents and/or brands.

1 | RESEARCH GRANT TYPE

ONE (1)research grant for candidates with master degree  with reference number BI|2024/497  is now available under the scope of project UNIFY – refª 2022.06780.PTDC, funded by fundação para ciência e a tecnoloGia  and under the following conditions:

2 | DURATION

THREE (3) months, starting in April 2024

-     Renewable, if the candidate is enrolled in a PhD program -  art. 6º, n.4 c)

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

subject to suitable performance within the period of the project, not exceeding the maximum period set by FCT for such grants – 4 years (included contract renewals)

 

-     Renewable, if the candidate is enrolled in a non-degree programme – art. 6º, n. 4 a)

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf  

subject to suitable performance within the period of the project, not exceeding the maximum period set by FCT for such grants – 1 year (included contract renewals)

 

3 | LEGISLATION

A fellowship contract will be celebrated according to:

Law 40/2004 of 18th of August (Scientific Research Fellow Status) and its successive amendments, including the amendments introduced by the Decree Law n. 123/2019 of 28 th of August 
https://dre.pt/web/guest/legislacao-consolidada/-/lc/124281176/201912061112/73740605/diploma/indice?lcq=estatuto+do+bolseiro ,
 

Regulations for Research Grants of the Foundation for Science and Technology in force

https://www.fct.pt/financiamento/programas-de-financiamento/bolsas/

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

https://dre.pt/dre/legislacao-consolidada/lei/2004-58216179

 

INESC-ID Lisboa Grant Regulations

https://www.inesc-id.pt/scholarship-regulations/

The fellowship contract is awarded on an exclusive dedication basis – art. 5 of Scientific Research Fellow Status and art. 16 of Regulations for Research Grants of the Foundation for Science and Technology.

4 | MONTHLY AMOUNT

The monthly amount of the grant 1259,64€ is in accordance with the values stipulated in the “Regulations for Research Grants of the Foundation for Science and Technology” in force https://www.fct.pt/wp-content/uploads/2024/02/Tabela-de-Valores-SMM_atualizacao-2024.pdf  and shall be rendered through a monthly bank transfer to an account held by the grantee.

5 | OBJECTIVES/WORKPLAN

This scholarship has as its main goal the application of the Unlimited Vector Extension (UVE) with Data Streaming Support to general-purpose high-performance hardware accelerators, such as Gemmini. In particular, the modeling of hardware accelerators supporting UVE is intended, by using widely accepted architectural simulators such as gem5. The integration of UVE with gem5-accel1 is intended as a starting point, followed by the modeling of an existing general-purpose hardware accelerator using this tool. In addition, Field-Programmable Gate Array (FPGA) prototyping is also envisaged in a later stage. The scholarship work will also include reporting the achieved results as a research article.

6 | SCIENTIFIC SUPERVISION

The activity will be supervised by Nuno Filipe Valentim Roma, Researcher at INESC-ID and Associate Professor at IST.

INESC ID will integrate the grantee in the research team of the scientific advisor.

7 | ADMISSION REQUIREMENTS

The candidates should have a MSc in Electrical and Computer Engineering, or related areas.

 

By the grant start date, the candidate must be enrolled in :

a PhD programme – art. 6º, n.1

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

or

a non-degree programme – art. 6º, n. 2

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

 

Preferential factors

Prospective applicants are expected to have strong knowledge of the following concepts:

• Central Processing Unit (CPU) and memory architectures;
• C/C++ and Python Programming Languages;
• Application Optimization: identify Regions of Interest (ROIs) in applications to accelerate and develop suitable custom hardware architectures to exploit those optimization opportunities;
• The gem5 architectural simulator: accurately model custom hardware architectures and integrate them with existing processing systems; build custom processing systems by correctly connecting and configuring different gem5 components; produce pertinent gem5 statistics for performance analysis or debug purposes; simulate processing systems using both System Emulation (SE) and Full System (FS) modes; use gem5 routines to defined ROIs for performance assessment purposes; resource to gem5 documentation to learn about how to use/modify/expand builtin modules;
• Operating Systems (OSs): map custom hardware accelerators into the CPU addressing space and develop device drivers to control those accelerators, as well as develop multi-threaded applications and use OS-specific (Linux) synchronization and communication mechanisms, such as locks, barriers, shared memory, etc. for benchmarking purposes;
• Hardware/Software Co-Design using FPGAs: describe hardware accelerators using Hardware Description Languages (HDLs), such as VHDL or Verilog; implement the necessary infrastructures to establish communication between the CPU and the hardware accelerators; and debug designs using proper hardware debugging tools such as the Integrated Logic Analyzer (ILA).

8 | EVALUATION CRITERIA AND COMMITTEE

The selection will be according to the following criteria:

[30%] Academic record

[40%] Past experience in architecture simulation using gem5

[30%] Past experience in architecture description using Verilog, and VHDL

 

If needed, the jury will interview the 3 best candidates. The interview result will weigh 50% towards the final evaluation score.

The jury may also decide not to assign the scholarship, if none of candidates meets the required conditions

 

Jury	Name	Professional Status	Institutions
President	Nuno Filipe Valentim Roma	Researcher / Associate Professor	INESC ID | Tecnico
Member	Pedro Filipe Zeferino Aidos Tomás	Researcher / Associate Professor	INESC ID | Tecnico
Member	Nuno F. S. Santos Moraes da Silva Neves	Researcher / Invited Assistant Researcher	INESC ID | Tecnico
Substitute member	Aleksandar Ilic	Researcher / Associate Professor	INESC ID | Tecnico
Substitute member	Leonel Augusto Pires Seabra de Sousa	Researcher / Full Professor	INESC ID | Tecnico

9 | COMPLAIN AND APPEAL DEADLINES AND PROCEDURES

The jury has the faculty not to select a candidate who does not prove the requirements mentioned in required education Level and research experience

 

The admitted and excluded candidates will be notified by email of the final ranking list, including the copy of the Preliminary Report of the jury.

 

Prior Hearing and Deadline for Final Decision: After being notified, candidates have 10 working days to submit, if applicable, a formal rebuttal.

 

After that period, the jury notifies the candidates of the Final Report.

 

Excluded applicants may complain about the jury's final report for 15 working days after notification or appeal the jury's decision to the INESC ID Board of Directors for 30 working days after notification.

 

According to the Portuguese Law, a disabled candidate has a preference when in equal classification, which prevails over any other legal preference. Candidates must declare their respective degree of disability, the type of disability and the means of communication / expression to be used in the selection process, under the law.

10 | FORMALISATION OF APPLICATIONS

Applications are formalised by sending an email to [email protected] with the documents stated bellow and in pdf form.  The application email should clearly state the reference of the research grant and project.
10.1	Single copy of official academic degree certificate in the required education level
	a) In the application submission, the candidates from portuguese education institutions may replace the copy of official academic degree certificate by a declaration of honour stating that they have the required academic degree.
		It is mandatory for the approval of the fellowship contract that the selected candidate presents a single copy of the official academic degree certificate, required in education level
	b) In the application submission, the candidates from foreigner education institutions may replace the copy of official academic degree certificate by a declaration of honour stating that they have the required academic degree.
	It is mandatory for the approval of the fellowship contract that the selected candidate presents a single copy of the official academic degree certificate, required in education level
10.2	Detailed list of grades (pdf form);
10.3	Proof of enrolment required on 7 a) or 7 b) (pdf form);
	In the application submission, the candidates may replace the proof of enrolment by a declaration of honour stating that they are/will be enrolled required in  7 a) or 7 b)
		It is mandatory for the approval of the fellowship contract that the selected candidate presents an official copy of the enrolment, required in 7 a) or 7 b)
10.4	Detailed curriculum vitae (pdf form);
10.5	Motivation letter explaining the interest in the position (pdf form);

11 | Application Dates

From		To
14-02-2024		08-03-2024

 

 

Requirements

Research Field

Engineering » Computer engineering

Education Level

Master Degree or equivalent

Research Field

Engineering » Electrical engineering

Education Level

Master Degree or equivalent

Skills/Qualifications

This scholarship has as its main goal the application of the Unlimited Vector Extension (UVE) with Data Streaming Support to general-purpose high-performance hardware accelerators, such as Gemmini. In particular, the modeling of hardware accelerators supporting UVE is intended, by using widely accepted architectural simulators such as gem5. The integration of UVE with gem5-accel1 is intended as a starting point, followed by the modeling of an existing general-purpose hardware accelerator using this tool. In addition, Field-Programmable Gate Array (FPGA) prototyping is also envisaged in a later stage. The scholarship work will also include reporting the achieved results as a research article.

Specific Requirements

The candidates should have a MSc in Electrical and Computer Engineering, or related areas.

 

By the grant start date, the candidate must be enrolled in :

a PhD programme – art. 6º, n.1

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

or

a non-degree programme – art. 6º, n. 2

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

Additional Information
Benefits

The monthly amount of the grant 1259,64€ is in accordance with the values stipulated in the “Regulations for Research Grants of the Foundation for Science and Technology” in force https://www.fct.pt/wp-content/uploads/2024/02/Tabela-de-Valores-SMM_atualizacao-2024.pdf  and shall be rendered through a monthly bank transfer to an account held by the grantee.

Eligibility criteria

The candidates should have a MSc in Electrical and Computer Engineering, or related areas.

 

By the grant start date, the candidate must be enrolled in :

a PhD programme – art. 6º, n.1

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

or

a non-degree programme – art. 6º, n. 2

https://files.dre.pt/2s/2019/12/241000000/0009100105.pdf

Selection process

The selection will be according to the following criteria:

[30%] Academic record

[40%] Past experience in architecture simulation using gem5

[30%] Past experience in architecture description using Verilog, and VHDL

 

If needed, the jury will interview the 3 best candidates. The interview result will weigh 50% towards the final evaluation score.

The jury may also decide not to assign the scholarship, if none of candidates meets the required conditions

Additional comments

Preferential factors

Prospective applicants are expected to have strong knowledge of the following concepts:

• Central Processing Unit (CPU) and memory architectures;
• C/C++ and Python Programming Languages;
• Application Optimization: identify Regions of Interest (ROIs) in applications to accelerate and develop suitable custom hardware architectures to exploit those optimization opportunities;
• The gem5 architectural simulator: accurately model custom hardware architectures and integrate them with existing processing systems; build custom processing systems by correctly connecting and configuring different gem5 components; produce pertinent gem5 statistics for performance analysis or debug purposes; simulate processing systems using both System Emulation (SE) and Full System (FS) modes; use gem5 routines to defined ROIs for performance assessment purposes; resource to gem5 documentation to learn about how to use/modify/expand builtin modules;
• Operating Systems (OSs): map custom hardware accelerators into the CPU addressing space and develop device drivers to control those accelerators, as well as develop multi-threaded applications and use OS-specific (Linux) synchronization and communication mechanisms, such as locks, barriers, shared memory, etc. for benchmarking purposes;
• Hardware/Software Co-Design using FPGAs: describe hardware accelerators using Hardware Description Languages (HDLs), such as VHDL or Verilog; implement the necessary infrastructures to establish communication between the CPU and the hardware accelerators; and debug designs using proper hardware debugging tools such as the Integrated Logic Analyzer (ILA).

Work Location(s)

Number of offers available

1

Company/Institute

INESC ID

Country

Portugal

State/Province

Lisbon

City

Lisbon

Postal Code

1000-029

Street

Rua Alves Redol, 9

Geofield

Where to apply

E-mail

[email protected]

Contact

State/Province

Lisboa

City

Lisboa

Website

http://www.inesc-id.pt

Street

Rua Alves Redol, 9

Postal Code

1000-029

E-Mail

[email protected]

STATUS: EXPIRED