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This PostDoc will be positioned at Prof. Bram Nauta's Integrated Circuit Design Group and requires the candidate to come up with new system architectures and circuit level techniques in the areas related to high-speed low-noise data converters specifically in the domain of wideband data acquisition, time-interleaved ADCs, noise-shaping ADCs and GS/s sigma-delta ADCs. Applicants must have published at least two Journal articles (2 JSSC or combination of JSSC and TCAS-1). The PostDoc contract will be initially for 15 months and can be extended for another year based upon performance review.
- We expect you to investigate bottlenecks related to speed, energy consumption and noise in realizing high-speed high-resolution data converters;
- We expect you to come up with new system architectures and circuit level techniques for realizing high-speed low-noise data converters that can further advance state-of-the-art by orders of magnitude.
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