PhD position on Compiler Design for Smart Edge Processors

We are seeking a highly skilled and motivated candidate to research and develop a high-quality optimizing compiler, including backend with code generation support for advanced Coarse Grain Reconfigurable Array (CGRA) targets. The CGRAs will support Deep Learning Networks, based on dynamic SNNs or ANNs.

Compared to existing solutions, energy efficiency needs to be improved by exploiting ILP, DLP (SIMD), an advanced memory hierarchy, data reuse, sparsity, quantization, etc. Application and Network dynamism must be exploited to further reduce energy consumption.

Project

The candidate will be working within the CONVOLVE project which aims to create the next generation of Edge-AI processing hardware. Unlike existing solutions, this hardware needs to support high throughput, reliable, and secure AI processing at ultra-low power (ULP), combined with a very short time to market.

With its strong legacy in edge solutions and open processing platforms, the EU is ideally positioned to become the leader in this edge-AI market. However, certain roadblocks keep the EU from assuming this leadership role: Edge processors need to become 100x more energy efficient; Their complexity demands automated design with 10x design-time reduction; They must be secure and reliable to get accepted; Finally, they should be flexible and powerful to support the rapidly evolving DL domain.

The CONVOLVE consortium includes some of Europe's strongest research groups and industries, covering the whole design stack and value chain. In a community effort, we will demonstrate Edge-AI computing in real-life vision and audio domains. By combining these innovative ULP and fast design solutions, CONVOLVE will, for the first time, enable reliable, smart, and energy-efficient edge-AI devices at a rapid time-to-market and low cost, and as such, opens the road for EU leadership in edge-processing.