2 Linguistics positions at Ecole Centrale de Lyon in France

PhD Ferroelectric Transistors (FeFET) Aware Logic Synthesis

production flow, the Synthesis takes in input the circuit model description, usually expressed in a hardware description language (e.g., VHDL, Verilog) and produces as output the gate level netlist for a given

Post-doctoral candidate on Bio-inspired hybrid laser smart texturing of SLIPS for anti-icing properties

graduated in a country where French/English is the first language, then you will need to demonstrate your French/English proficiency by having passed IELTS or TOEFL. The minimum overall score for IELTS is at