Context
The performance of the processors used in scientific computing and for machine learning applications continues to improve. One of the primary techniques for achieving performance consists of exploiting parallelism; however, this approach works well only when the data is regular. Many real-world problems involve sparse data sets, making it difficult to fully exploit parallel hardware. Furthermore, transferring data from the memory sub-system to the processor is often the limiting factor for performance, due both to bandwidth and power constraints. For problems with sparse data, optimizing the memory accesses is more challenging as the access patterns are irregular. There is a need for new hardware support for the processing of sparse data, as demonstrated by emerging GPUs that are now providing such hardware solutions.
Summary of the Thesis Topic
In this thesis, the candidate will start by reviewing the state of the art in terms of memory and cache systems for high-performance processors, including an in-depth study of the vast literature on representations for sparse matrices and sparse data. The candidate will then propose new architectures for a memory sub-systems optimized for this class of problem, including analyzing the interactions with a conventional cache hierarchy. The solutions may involve direct hardware support for specific data-structures, data compression or other techniques. The architectures will first be evaluated using a light-weight prototype and the most promising ones will be implemented on an high-end FPGA, integrated with a RISC-V processor optimized for scientific computing.
About the CEA and LIST
The CEA (French Commission for Atomic and Renewable Energy) is a public research institute. It plays an important role in the research, development and innovation community. The CEA has four missions: security and defense, nuclear energy (fission and fusion), technology research for industry and fundamental research. With 16 000 employees, including technicians, engineers, researchers and support personnel, the CEA is involved in numerous research projects in collaboration with both academic and industrial partners.
In the section of the CEA focused on technology research for industry, the LIST institute is focused on intelligent digital systems. This institute has a culture of innovation and has as a mission to transfer these technologies to industrial partners. The DSCIN department specializes in complex digital and embedded systems for Artificial Intelligence (AI), High-Performance Computing (HPC) and Cyber security applications.
About the LSTA Laboratory
LSTA : The focus of the LSTA laboratory is on the design and implementation of high-performance multi-core architectures and accelerators. These systems are built using the latest technologies including advanced CMOS (7 nm), 2.5D/3D integration, non-volatile memories and FPGAs. These systems are used for High Performance Computing (HPC) applications, AI (Artificial Intelligence) applications and quantum computing (digital control of quantum CMOS circuits). This laboratory is located in Grenoble.
For the academic registration, the candidate will be affiliated with the UGA (University of Grenoble Alps). The academic supervisor is in the SLS (System Level Synthesis) team at the TIMA laboratory. This team is specialised in parallel computer architectures including the associated software infra-structure.
Contacts
Supervisor : Adrian EVANS and Yves DURAND
Email : [email protected] and [email protected]
Academic Supervisor : Frédéric ROUSSEAU
Email : [email protected]
Required Background
A Master’s degree in computer science, computer or electrical engineering. An experience with processor design or with RISC-V is a plus. It is important to have an interest in numerical analysis and matrix calculations. Critical thinking, the ability to code and to perform hardware development (Verilog) are essential. It is not essential to speak French.
To Apply
Please send your application by email including:
- A detailed CV
- A cover letter
- Marks and ranking for the three previous academic years
- Two references
Contact
Adrian EVANS
CEA DRT/DSCIN/LSTA
17 avenu des Martyrs
38054 Grenoble CEDEX
Téléphone: +33.4.38.78.041.41
More infomation : https://instn.cea.fr/these/conception-dun-systeme-memoire-pour-traitement-de-donnees-creuses/
Start and End Dates : October 2022 – October 2025