17 Apr 2024
Job Information
- Organisation/Company
Ecole centrale de lyon- Department
EEA- Research Field
Technology » Future technology
Computer science » Computer hardware
Physics » Electronics- Researcher Profile
First Stage Researcher (R1)- Country
France- Application Deadline
3 May 2024 - 23:59 (Europe/Paris)- Type of Contract
Temporary- Job Status
Full-time- Is the job funded through the EU Research Framework Programme?
Not funded by an EU programme- Is the Job related to staff position within a Research Infrastructure?
No
Offer Description
Scientific context:
Emerging technologies such as ferroelectric capacitors (FeCap) and transistors (FeFET, FemFET) are among the best technological options to overcome the bottleneck of classical computing architectures. Indeed, the main advantage of non-volatile emerging technologies lies in the possibility to change the computing paradigm, i.e. perform computing directly inside the memory or the computing unit’s embedded memory. This allows a drastic reduction of data transfers thus increasing both the energy efficiency and the computation speed.
The promises in terms of energy and computing efficiency make these technologies extremely appealing for Internet of Things and embedded artificial intelligence applications. For both applications, high security level is mandatory to protect personal data and intellectual property of used devices. Physical Unclonable Functions (PUF) is today a hardware security primitive which can be used for both requirements. A PUF is a hardware unit capable of leveraging the manufacturing process variability that inevitably occurs during the fabrication of integrated circuit. In consequence, PUFs can be used to create a unique IC (Integrated Circuit) identifier of but also cryptographic keys under certain conditions.
Thesis objectives:
The main objective of this thesis is to develop a new PUF based on Ferroelectric technologies and evaluate it according to the state of the art both in terms of quality and security attack. In addition, PUF design are often close to True Random Number Generator (TRNG) because of noise extraction. Indeed, when a PUF try to extract static noise (manufacturing variations), TRNG extract random noise (electronic noise, thermal noise, jitter, …). Another objective of this thesis will be to study the possibility
to create a dual PUF/TRNG structure. Finally, the hardware security primitive will have to be tested and evaluated.
Requirements
- Research Field
- Other
- Education Level
- Master Degree or equivalent
Skills/Qualifications
- Experience in micro-electronic circuit design and modelling.
- Software and languages under consideration of the computation, simulation, and hardware design:
- Cadence, VHDL, Verilog, C/C++, Python.
- Knowledge basic functions in hardware security (PUF, TRNG, …) will be also appreciated.
- Knowledge in statistical evaluation will be appreciated.
- The candidate should be curious, highly motivated, and flexible to address a highly inter-disciplinary
- project.
- Good English skills, writing and speaking, are needed.
- Research Field
- Technology » Future technologyComputer science » Computer hardware
Internal Application form(s) needed
PhD_offer_EEA_INL_pub.pdf
English
(725.52 KB - PDF)
Download
Additional Information
Work Location(s)
- Number of offers available
- 1
- Company/Institute
- Institute of nanotechnologies of Lyon
- Country
- France
- City
- Ecully
- Postal Code
- 69134
- Street
- 36 Av. de Guy de Collongue
- Geofield
Where to apply
[email protected]
Contact
- City
Ecully- Website
https://www.ec-lyon.fr/
https://inl.cnrs.fr/- Street
36 Av. de Guy de Collongue- Postal Code
69134
STATUS: EXPIRED