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We are looking for a co-design engineer for future computing architectures in HPC. This position, in a fixed-term contract, is based at the Nano-Innov site of Paris-Saclay, Essonne (91). As part of
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Inria, the French national research institute for the digital sciences | Grenoble, Rhone Alpes | France | 2 months ago
. The primary mission is to lead the architectural design and strategic development of the compilation system. The candidate will drive the definition and standardization of high-level intermediate
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, leading three ambitious, parallel research axes: pushing model accuracy on systems of several thousand atoms with an IWAE architecture; equipping it with the ability to quantify its own uncertainty — a
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verification, RTL design and digital circuits, processor architectures (RISC-V experience is a plus), embedded software. The position offers an opportunity to work at the intersection of hardware security