Analog Design Engineer, Staff

5 Mar 2024
Job Information

Organisation/Company

Synopsys

Research Field

Computer science » Other

Researcher Profile

First Stage Researcher (R1)

Country

United States

Application Deadline

31 Mar 2024 - 00:00 (UTC)

Type of Contract

To be defined

Job Status

Negotiable

Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme

Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

We're looking for Analog Design Engineer to join our team. Does this sound like a good role for you?

In this role, you will work on the design, development, and refinement of Multi-Gbps PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team, developing high speed analog integrated circuits in the latest FinFET process nodes. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Job Responsibilities
Investigate and contribute developing circuit architectures that address architectural bottlenecks and drive to revolutionary improvements in power, area and performance targets.
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
Document design features and test plans.
Consult on the overall electrical characterization of the SerDes IP product. Investigate customer silicon data for design enhancements. Propose solutions for post-silicon design updates.

Job Requirements
PhD with 2+ years, or MSc with 4+ years of practical analog IC design experience. Degree in Electrical Engineering or similar.
Deep knowledge of transistor level circuit design, with particular focus on high-speed analog design
Design experience with at least one sub-circuit relevant to SerDes: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC

Experience in the following aspects of the design process is studied as a plus:
Expertise of layout effects (i.e. matching, reliability, proximity effects, etc.).
Knowledgeable in Verilog-A for analog behavioral modeling
Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is a nice to have.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Requirements
Additional Information

Website for additional job details

https://www.hipeac.net/jobs/14563/analog-design-engineer-staff/

Work Location(s)

Number of offers available

1

Company/Institute

Synopsys

Country

Italy

City

Pavia

Geofield

Where to apply

Website

https://careers.synopsys.com/job/pavia/analog-design-engineer/44408/55683202432

Contact

City

Mountain View, CA

Website

https://www.youtube.com/user/synopsys
https://www.synopsys.com/
https://twitter.com/synopsys
https://www.linkedin.com/company/synopsys

E-Mail

[email protected]

STATUS: EXPIRED