Principal Analog Design Engineer (Memory/Audio Interface)

Updated: about 1 month ago
Deadline: 30 Apr 2024

13 Mar 2024
Job Information
Organisation/Company

Cadence EMEA
Research Field

Computer science » Other
Researcher Profile

Established Researcher (R3)
Country

Germany
Application Deadline

30 Apr 2024 - 00:00 (UTC)
Type of Contract

To be defined
Job Status

Negotiable
Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme
Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

Job Overview:

Lead Analog and Mixed Signal design of high speed memory interface analog components used in state-of-the-art DDR memory interface PHYs in leading edge technology nodes. Consisting of blocks such as IOs, amplifiers, comparators, drivers, duty cycle correctors, PLLs, DLLs, level shifters, etc. in advanced IC nodes in volume production.

As Principal Design Engineer, you will provide technical direction and coordination to the analog IC design team and Identify opportunities to advance technology of analog design and participate in strategic internal analog IP development.


Requirements
Additional Information
Website for additional job details

https://www.hipeac.net/jobs/14592/principal-analog-design-engineer-memoryaudio-…

Work Location(s)
Number of offers available
1
Company/Institute
Cadence EMEA
Country
Ireland
City
Cork
Geofield


Where to apply
Website

https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/details/Principal-…

Contact
City

Several locations in Germany, France, Italy, Israel, Sweden, UK
Website

https://www.cadence.com/content/cadence-www/global/en_US/home/training/emea.html
https://twitter.com/Cadence_EMEA
E-Mail

[email protected]

STATUS: EXPIRED

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