Memory Subsystem Architecture Researcher/GPU Memory Subsytem Architect

Enable and explore memory subsystem architectures for next generation AI/HPC workloads under a technology, architecture, application co-design regime.

The Compute System Architecture (CSA) unit at imec desires to build zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance. 

The memory subsystem of a next generation AI/HPC system architecture --- as it interacts with the application workload, the program execution model and compute nodes and the rest of the uncore architecture --- has a high impact on the system performance and energy efficiency. As a memory subsytem researcher / architect, you are part of a team developing simulation infrastructures to model next generation AI/HPC systems to enable PPA based co-design across technology, architecture, and workloads. Your role spans a combination of the following responsibilities: you develop and integrate models (cycle level / functional / power / area) of relevant components of the memory subsystem (e.g., SSD/DRAM/...3D-SRAM to Cache/Directory Controllers, ...) in our simulation framework;  you evaluate / demonstrate the impact of workloads on memory subsystem technology / design choices by designing appropriate experiments; you work with component/other-subsystem/workload modelling architects and propose and evaluate architectural innovations; you will interface with RTL designers implementing the memory subsystem.