2 hardware PhD positions at CNRS

M/F PhD offer on Spike Sorting algorithm implementation on Hybrid FPGA/ASIC platform for next generation of Brain Computer interfaces

CNRS | Villeneuve la Garenne, le de France | France | 3 months ago

jointly operated by CNRS and the University of Sherbrooke. LN2 provides a unique environment for research at the intersection of nanotechnology, advanced microelectronics, and hardware-based artificial

PhD student (M/F) Frugal diagnostics and fault isolation in reconfigurable multi-source microgrids

CNRS | Toulouse, Midi Pyrenees | France | about 2 months ago

. Experimental Validation • Validation in real-time simulation. • Validation on HIL/PHIL (Hardware-in-the-Loop and Power-Hardware-in-the-Loop) platforms. • Performance evaluation on scenarios representative