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modernization efforts by developing EPICS applications to support embedded and FPGA based systems. Help upgrade existing EPICS applications and user interfaces. Complete verification, deployment, and
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computing, or hardware reliability. Experience with GPU, FPGA, embedded, or specialized AI accelerator platforms. Experience with scientific programming, benchmarking, or reproducible experimentation
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multiple projects Preferred: Experience with educational technology development and web programming LAMP stack design and implementation experience Knowledge of GPU and FPGA cluster management Experience
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Proficiency in at least one programming language (e.g. Python, C++) ▪ FPGA programming experience ▪ Interest in hands ‑ on experimentation and hardware prototyping The following points
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Multiple Tenure-Track Assistant Professor Positions in Microelectronics, Circuits and Systems Design
sequence; Analog IC Design; sensor/measurement laboratory modules; mixed-signal design projects. Digital VLSI and AI Hardware Systems Key research areas: ASIC / FPGA design flows; AI/edge accelerators
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automation. FPGA programming. Programming, numerical modelling, data analysis and control of complex experimental systems. Ability to work independently and as part of a team. Excellent communication skills
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power electronics, motor drives, control and signal processing. Specialised training on relevant software will be made available (FPGA programming, Real-time modelling tools e.g. Opal-RT, Speedgoat
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doctoral candidates with strong theoretical foundations and practical expertise to drive innovation in Europe’s future telecommunications landscape. More information about ANCHOR network can be found https
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Posting Number req26485 Department Steward Observatory Department Website Link https://astro.arizona.edu/ Location Tucson Campus Address Tucson, AZ USA Position Highlights Steward Observatory has an
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sequence; Analog IC Design; sensor/measurement laboratory modules; mixed-signal design projects. Digital VLSI and AI Hardware Systems Key research areas: ASIC / FPGA design flows; AI/edge accelerators