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field effects transistors (CMOSFET) [2]. The use of atomic thick material comes with new challenges. The bond free surfaces challenge the gate dielectric deposition process with classical techniques. Also
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processing for nanoelectronics applications Apply 2D layered Transition Metal Di-Chalcogenides (TMDCs) are envisioned for replacing silicon in advanced CMOS logic technology nodes, in the form of stacked
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from which a wide range of information such as orientation, phase, thickness, stacking, strain, etc., can be extracted. Consequently, there is a growing need for fast and automated processing
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team with various backgrounds in materials and deposition techniques, state of the art 200mm and 300mm process lines, laboratories, device learning and modelling. The PhD candidate will be part of
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nucleate and how they orient during the CVD process. You can propose various strategies to alter the chemical reactivity of starting surface by surface functionalization, and to introduce a relief or
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deposition processes of homo- and heterostructures with monolayer thickness control that can be integrated into future sub-nanometer devices such as gate-all-around nanosheet field effect transistors (FETs
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research domains: 6G and Wireless Internet of Things communication Automotive CMOS and beyond CMOS 3D system integration Advanced nano-interconnects Advanced patterning and key process steps High-speed