2 PROCTER GAMBLE EUROCOR NV PhD scholarships at Ecole Centrale de Lyon

PhD Ferroelectric Transistors (FeFET) Aware Logic Synthesis

voltages and timing dependencies of the ferroelectric NV elements. 2. Design of logic/sequential Elements with Mixed Volatile/Non-volatile Mode (M6 to M12) • This task will start from the state-of-the-art

PhD Project DAC Analysis and synthesis of Anomaly Detectors under Critical-time constraints

specification. This is due in particular to the difficulty of assessing the risk, and especially the likelihood, of an attack due to the heterogeneity of attackers, both in terms of objectives and resources