27 Mar 2024
Job Information
- Organisation/Company
Inria Rennes- Research Field
Computer science » Other- Researcher Profile
First Stage Researcher (R1)- Country
France- Application Deadline
30 Apr 2024 - 00:00 (UTC)- Type of Contract
To be defined- Job Status
Negotiable- Is the job funded through the EU Research Framework Programme?
Not funded by an EU programme- Is the Job related to staff position within a Research Infrastructure?
No
Offer Description
Reliability improvement of Risc-V based multiprocessor architectures
TARAN - IRISA research team
Keywords: open and free instruction set architecture, increased operability time, network-on-chip, multiprocessor system, fault tolerance.
Context
Today's computing hardware architectures have to satisfy a number of scientific and societal challenges. From a scientific perspective, improving performance and energy efficiency is undoubtedly the primary objective of their evolution. Technology evolution also enables the integration of ever more transistors that facilitates the design of parallel architectures based on multicore paradigm. To exchange information between computing cores, these architectures are organized around a Network-on-Chip (NoC) communication medium providing flexibility and efficiency [3,4].
From a societal point of view, reducing the energy impact of consumer electronics and preventing obsolescence are becoming increasingly important. It means that they should be integrated during the early design phase. Integrating these constraints as early as possible is intended to enable the design of circuits that are efficient, fault-tolerant and therefore sustainable over time [5, 6]. Indeed, the faults can be caused by (a) the context in which the circuit is used (electromagnetic radiation, particles, etc.), but also (b) the aging of the component [7]. In response to these challenges, the design of open, fault-resilient computing architectures is a line of research that needs to be developed and expanded, in order to offer sustainable electronics that nevertheless meet application requirements.
Proposed research work
The work proposed in this PhD addresses these issues and focuses on the permanent fault tolerance of on-chip networks embedded in open multicore architectures. The main objective is to propose architectures that are more resilient to faults, particularly those related to premature aging, which will make it possible to prevent obsolescence by extending the lifetime of electronic equipment in general.
While many works have addressed the robustification of processing cores [1,2], we propose to focus our work on the interconnection network [8, 9]. Based on the open and free architecture of the RISC-V instruction set, we propose to investigate the coupling between the computing cores and the associated routers of the on-chip network. Our proposal consists in redesigning the router of an NoC as a hardware extension of the core, and to control it through the extension of the core's instruction set. The router will be equipped with fault detection and bypass capabilities.
From the computing core's point of view, the router will be considered a specialized hardware accelerator, and the extended instruction set will provide operating system flexibility to react to faults. Local faults, or even more distant faults, obtained by the propagation of information from router to router, can be detected and analyzed in order to activate the appropriate strategies to meet the application's constraints, according to the capabilities of the faulty system. The techniques we will propose will therefore make it possible to combine i) performance, through strong coupling between the two elements studied (processing core and router), and ii) preventing circuit obsolescence by ensuring that the architecture model has resilient capabilities and devices. Finally, based on an open, free RISC-V architecture, this work will ensure the durability of the systems designed, and their independence from changes in commercial architectures.
This PhD project is consistent with the TARAN team's research areas, since it addresses the design of fault-tolerant, low-power and open-access multicore systems. The proposed work will contribute to one of the major societal issues in electronics today: the durability of hardware, particularly processor-based systems. In addition, this work will reinforce the TARAN team's expertise as a major contributor to the development of open architectures, and thus to the sustainability and independence of tomorrow's electronics.
Application and profile
To perform these tasks, you must have a good knowledge of hardware design, system-on-chip and network-on-chip architectures, and knowledge of RISC-V architecture is a plus. These skills are generally provided as part of training courses in embedded systems (at master's or engineering level).
To apply for this position, please send a CV, a covering letter and your M1 and M2 results to: [email protected] , [email protected] .
Application deadline: April 30, 2024
Location of thesis work
The thesis work will be carried out at the Lannion site of the Inria TARAN project team, and more specifically on the site of ENSSAT (École Nationale Supérieure des Sciences Appliquées et de Technologie). If so desired, the person recruited will be able to teach digital electronics to engineering students at ENSSAT and/or senior technicians at the Lannion IUT.
Start of work: October 2024
Contacts:
Daniel CHILLET ,
Bertrand LE GAL
References
Requirements
Additional Information
- Website for additional job details
https://www.hipeac.net/jobs/14611/phd-proposal/
Work Location(s)
- Number of offers available
- 1
- Company/Institute
- Inria Rennes
- Country
- France
- City
- Lannion
- Geofield
Where to apply
[email protected]
Contact
- City
Rennes- Website
https://www.inria.fr/fr/centre-inria-universite-rennes
https://twitter.com/inria
STATUS: EXPIRED