Sort by
Refine Your Search
-
wiring that takes care of the interconnection between logic standard cells at processor level. In advanced nodes, the most critical interconnect layers will be reduced to 20 nm pitches and below, requiring
-
documentation Experience with synthesis and physical design tool flows (Cadence Genus/Innovus, or Synopsys Fusion/DC/ICC) is a must You care deeply about customer satisfaction and quality of the delivered results
Searches related to Management
Enter an email to receive alerts for Management positions