SEU Detection and Mitigation for Satellite Based FPGA On-board Processing, University of New South Wales.

Future earth observation missions are expected to have very high data rate and processing requirements. The next generation of on-board processing is also required to be flexible and reprogrammable in-orbit and during active service. The research work is concerned with proposing novel solutions to mitigate effects of the SEUs on FPGAs. Research will start with analysing fault injection methods to model and characterise SEU effects on COTS FPGAs. This will be followed by developing innovative low-complexity methods for detecting and localizing SBU/MBUs due to SEUs in the system. The research will culminate in the development of novel run-time low-complexity SEU mitigation techniques. Expected outcome of this research is to have a system which detects and mitigates the SEU effects during run-time without user intervention in an autonomous way, thereby paving the way for widespread use of FPGAs for space applications.

This scholarship is offered once only to one person. Dates when to submit scholarship application are not specified.

The value of this scholarship is AUD23728 (total may vary). This award is to be used for living expenses. This scholarship is paid fortnightly for the period of 3 and a half years.

This scholarship is for one of the following fields of research: Aerospace engineering, Computer hardware, Electrical and electronic engineering or ENGINEERING AND TECHNOLOGY.

This scholarship is for study in Australia for those who have achieved Bachelor Degree.

To apply for this scholarship you must apply directly to the university. You can download a PDF with more information about the scholarship here. Terms and conditions are subject to change. Always confirm details with scholarship provider before applying.