4 master scholarships at Ecole Centrale de Lyon

PhD thesis in System, Control and Signal Processing - Robust System Optimization for better energy efficiency in Advanced Silicon Systems

, specialized engineers, masters and doctoral students. With the Groupe des Écoles Centrale, it has three international locations. The training provided benefits from the excellence of the research carried out in

PhD - Towards efficient analysis and synthesis of Heterogeneous Interconnected Systems : application to signal estimation

and professional institution. Mmember of the Ecoles Centrales group and the Écoles Nationales d’Ingénieurs network, ECL trains high-level generalist engineers, specialized engineers, masters students

PhD Ferroelectric Transistors (FeFET) Aware Logic Synthesis

layout floorplan. The Synthesis flow is mainly composed of two main steps: (i) Logic synthesis and optimization and (ii) Place&Route. As defined in [1], the overall problem of logic synthesis is the one

PhD Project DAC Analysis and synthesis of Anomaly Detectors under Critical-time constraints

and professional institution. Mmember of the Ecoles Centrales group and the Écoles Nationales d’Ingénieurs network, ECL trains high-level generalist engineers, specialized engineers, masters students