Networks-on-Chip Strategy for Scalable Neuromorphic Hardware

Ulster University, United Kingdom

Updated: 4 months ago
Location: Coleraine, NORTHERN IRELAND
Deadline: The position may have been removed or expired!

These scholarships will cover full-time PhD tuition fees for three years (subject to satisfactory academic performance) and will provide a £900 per annum research training support grant (RTSG) to help support the PhD researcher.

Applicants who already hold a doctoral degree or who have been registered on a programme of research leading to the award of a doctoral degree on a full-time basis for more than one year (or part-time equivalent) are NOT eligible to apply for an award.

Please note: you will automatically be entered into the competition for the Full Award, unless you state otherwise in your application.

The scholarship will cover tuition fees at the Home rate and a maintenance allowance of £19,000 (tbc) per annum for three years (subject to satisfactory academic performance).

This scholarship also comes with £900 per annum for three years as a research training support grant (RTSG) allocation to help support the PhD researcher.


[1] Y. Qiu et al., "A Novel Ring-based Small-World NoC for Neuromorphic Processor," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 234-241, 2021

[2] S Carrillo, J Harkin, LJ McDaid, F Morgan, S Pande et al. “Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations”, IEEE Transactions on Parallel and Distributed Systems 24 (12), pp. 2451-2461, 2012.

[3] J Liu, J Harkin, LP Maguire, LJ McDaid, JJ Wade: “SPANNER: A self-repairing spiking neural network hardware architecture”, IEEE transactions on neural networks and learning systems 29 (4), pp.1287-1300, 2017.

[4] Karim, J Harkin, L McDaid, B Gardiner, J Liu, "AstroByte: Multi-FPGA architecture for accelerated simulations of spiking astrocyte neural networks", Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020

[5] G Martin, J Harkin, LJ McDaid, JJ Wade, J Liu, “On‐chip communication for neuro‐glia networks”, IET Computers & Digital Techniques 12 (4), pp.130-138, 2018


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