PhD/Post-doc position on workload acceleration using SmartNICs

Updated: about 2 months ago
Deadline: 16 Mar 2024

1 Mar 2024
Job Information
Organisation/Company

Sapienza University of Rome
Research Field

Computer science » Computer architecture
Researcher Profile

Recognised Researcher (R2)
First Stage Researcher (R1)
Country

Italy
Application Deadline

16 Mar 2024 - 00:00 (UTC)
Type of Contract

To be defined
Job Status

Negotiable
Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme
Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

Smart Network Interface Cards (SmartNICs) offer unprecedented opportunities for achieving high performance and reduced CPU utilization in a wide range of scenarios spanning from datacenter networking to AI/ML and HPC applications. However, the resource constraints of these devices pose significant challenges for their effective and efficient exploitation. We seek a highly motivated Ph.D./post-doc researcher to explore the design of acceleration of network functions and HPC applications exploiting architectures such as last-generation NVIDIA BlueField DPUs or AMD-Xilinx FPGA-based Alveo SmartNICs.

Research Focus:

  • Investigate the theoretical limits and practical benefits of existing SmartNICs.
  • Assess the computational and memory overheads associated with implementing HPC primitives (e.g., collective operations) and applications on SmartNICs.
  • Explore the tradeoffs between fully- and partially offloaded algorithms, especially those used in ML training scenarios (e.g., gradient aggregation, sparsification, and quantization).
  • Explore the tradeoffs in terms of performance and flexibility between on-path and off-path solutions.

Research Activities:

  • Conduct comparative evaluations to benchmark the performance of different SmartNIC architectures, identify the limitations of the current generation, and hopefully contribute to designing the architecture of next-generation ones.
  • Develop innovative algorithms tailored for SmartNICs to optimize processing efficiency and memory utilization.
  • Integrate SmartNIC offload in machine learning frameworks such as PyTorch.
  • Collaborate closely with industry partners, including NVIDIA, to leverage expertise and resources in SmartNIC and DPU technologies.

Research Environment: This research will be conducted at the Dipartimento di Informatica of Università di Roma – La Sapienza. The university provides a stimulating academic environment conducive to interdisciplinary research and innovation in networking and computer science.

Interested candidates are encouraged to contact Prof. Salvatore Pontarelli at [email protected] or Prof. Daniele De Sensi at [email protected] for further information and application instructions.


Requirements
Additional Information
Website for additional job details

https://www.hipeac.net/jobs/14559/phdpost-doc-position-on-workload-acceleration…

Work Location(s)
Number of offers available
1
Company/Institute
Sapienza University of Rome
Country
Italy
City
Rome
Geofield


Where to apply
Website

https://web.uniroma1.it/trasparenza/sites/default/files/Bando%2004%20AR_4.pdf

Contact
City

Rome
Website

https://www.uniroma1.it/it/
https://twitter.com/Sapienzaroma

STATUS: EXPIRED

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