Application Engineer (Design For Test)

Cadence EMEA, Germany

Updated: about 1 month ago
Deadline: 30 Apr 2024

13 Mar 2024
Job Information
Organisation/Company

Cadence EMEA
Research Field

Computer science » Other
Researcher Profile

Established Researcher (R3)
Country

Germany
Application Deadline

30 Apr 2024 - 00:00 (UTC)
Type of Contract

To be defined
Job Status

Negotiable
Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme
Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for an Application Engineer in DFT (Design For Test)

This is an excellent opportunity to work on challenging and complex SoC projects with Cadence customers in the semiconductor domain.

The Application Engineer will:

  • Provide high level of technical customer support for our products related to digital Design For Test.
  • Identify and track technical issues in Customers’ DFT design environment, prioritize these issues considering both Customer's & Cadence's needs and drive their resolution.
  • Assist the Customer with DFT flow development, e.g. improve existing design methodologies, develop new methodologies that leverage Cadence tools & services
  • Support technical evaluations (including Beta evaluations with Cadence R&D and the customer) of new digital EDA tools, flows and methodologies.
  • Provide direct contribution to key design projects, e.g. be responsible for driving Cadence DFT for key tasks on these projects.
  • Develop and maintain technical and soft skills to be seen as a trusted EDA tool specialist with a deep knowledge in Cadence's DFT tools.
    Work with the Cadence Sales team to identify additional sales opportunities.

    The Application Engineer will:

  • Have good understanding of DFT concepts and methodologies (ATPG, SCAN, BIST, …)
  • Have some knowledge on our SW tools: Modus, Genus, or similar tools from other EDA vendors.
  • Have excellent communication and problem-solving skills
  • Be prepared to visit Cadence customers in Southern Europe (France, Italy, Switzerland, …)
  • Experience in digital DFT design and possibly some of the following disciplines: Synthesis , STA, RTL design and verification, CAD support for Digital IC Design and related flows
  • Good communication skills; Excellent team spirit
  • Fluent in English
  • 2 to 4 years of experience in microelectronics/EDA industry
  • Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.

    We’re doing work that matters. Help us solve what others can’t.


    • Requirements
    Additional Information
    Website for additional job details

    https://www.hipeac.net/jobs/14591/application-engineer-design-for-test/

    Work Location(s)
    Number of offers available
    1
    Company/Institute
    Cadence EMEA
    Country
    Italy
    City
    Milan
    Geofield


    Where to apply
    Website

    https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/details/Applicatio…

    Contact
    City

    Several locations in Germany, France, Italy, Israel, Sweden, UK
    Website

    https://www.cadence.com/content/cadence-www/global/en_US/home/training/emea.html
    https://twitter.com/Cadence_EMEA
    E-Mail

    [email protected]

    STATUS: EXPIRED

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